This invention relates to information transfer systems for data processing systems and more particularly to a more efficient system of this nature having improved performance in relation to the amount of circuitry or pin count required.
Systems of this nature have been described heretofore wherein a central processing unit is interconnected with various subsystems such as storage devices, input/output devices such as printers, or other peripheral devices, the systems predominantly accomplishing transfer of information including data and commands among the various elements in the system by utilizing bus structures that are designed to accommodate the typical data byte or word configuration used in the system. In some cases, fewer transfer lines have been utilized by making use of a serializing/deserializing technique.
In recent years, there has been a trend to increase the density of circuits utilized in data processing systems. This has been accomplished by making use of rather effective technologies such as large scale integration (LSI) or very large scale integration (VLSI) techniques that are known in the art. By using these technologies, the cost of circuits and hence the cost of data processing systems has been considerably reduced.
The advent of processors on a single chip with a multitude of circuits has been a significant development in the past few years. Such a chip has a very high density of circuits in relation to its physical size. Along with that higher density, certain constraints are encountered in a system making use of such a chip in establishing interconnection of the circuits with external devices with which the processor communicates. In order to justify the cost of the chip, it is desirable to utilize as many of the circuits on the chip as possible, or practically all of them, if possible. On the other hand, while the number of pins available on the chip for interconnection to other elements in the system may remain constant, the number of circuits to be interconnected through the pins has greatly increased. It is therefore desirable to utilize the pins that are available in a more efficient manner to handle all of the command and data transfer requirements of the system.
The primary objective of the present invention is to accomplish transfer of data in either of two directions by a more efficient use of the available pins on a processor chip or card.